1. Field of the Invention
The present invention relates to an image signal processing apparatus and method and an image display apparatus and method. In particular, the invention is suitably applied to various display apparatus such as EL displays, plasma displays, and electron beam emission type fluorescent displays.
2. Description of the Related Art
FIG. 15 shows the configuration of a conventional display apparatus, more specifically, a spontaneous light emission type image display apparatus having pixels each being a combination of an electron-emitting element and a light emitter (phosphor) that emits light as it receives electrons from the electron-emitting element.
The conventional display apparatus is mainly composed of a display panel 1, a scanning driving unit 2, a modulation driving unit 3, a sync separation unit 4, an AD converter 5, a control unit 6, and an image processing unit 7. The control unit 6 is a microcomputer, a logic circuit, or the like.
The display panel 1 displays an image using surface conduction electron-emitting elements. Row scan-wiring lines Dx1–Dxm and column modulation lines Dy1–Dyn are arranged in matrix form, and electron-emitting elements (not shown) are located at their crossing points. As such, the display panel 1 is equipped with m-row/n-column electron-emitting elements. Each electron-emitting element, which emits electrons while a current flows through it, has a nonlinear characteristic as shown in FIG. 16. For example, whereas electrons are emitted when a voltage 16 V is applied to the element, almost no electrons are emitted when a voltage 8 V is applied to it. Emitted electrons are accelerated by an accelerating means (not shown) and collide with a phosphor screen (not shown) to cause light emission. That is, although the element emits light when supplied with 16 V, it does not emit light when supplied with 8 V, that is, a half of the former voltage. Therefore, as shown in FIG. 17, this enables passive matrix driving.
The scanning driving unit 2 is composed of changeover switches 22, a selection potential generation unit 23, and a non-selection potential generation unit 24.
The modulation driving unit 3 is composed of a shift register 31, a latch 32, a pulse width modulation circuit 33, and a drive amplifier 34.
Reference symbol S1 denotes an analog video signal that is input to the apparatus. Reference symbol S2 denotes a sync signal that is separated from the analog video signal S1. Reference symbol S3 denotes a digital video signal obtained by sampling the analog video signal S1 with the AD converter 5. Reference symbol S4 denotes a display signal obtained by performing image processing on the digital video signal obtained S3. Reference symbol S5 denotes a conversion timing signal that is supplied to the AD converter 5. Reference symbol S6 denotes an image processing control signal to be used for controlling the signal processing unit 7. Reference symbol S7 denotes a video clock signal to be used for controlling the operation of the shift register 31. Reference symbol S8 denotes a modulation control signal to be used for controlling the operation of the modulation driving unit 3. Reference symbol S9 denotes a PWM clock as a reference of operation of the pulse width modulation circuit 33. Reference symbol S10 denotes a scanning control signal to be used for controlling the operation of the scanning driving unit 2.
The sync signal S2 that is extracted by the sync separation unit 4 from the analog video signal S1 that is input to the apparatus is input to the control unit 6.
The control unit 6 generates the control signals S5–S10 on the basis of the sync signal S2.
The AD converter 5 samples the analog video signal S1 according to the conversion timing signal S5 and outputs the digital video signal S3.
The image processing unit 7 input the digital video signal S3 performs image processing such as image adjustments and a resolution conversion on the digital video signal S3, and outputs the display signal S4.
The operation that the scanning driving unit 2 and the modulation driving unit 3 drive the display panel 1 will be described below. FIG. 18 shows timing of this operation.
In the modulation driving unit 3, data of the display signal S4 are sequentially input to the shift register 13 in synchronism with the video clock signal S7 and display data are held by the latch 14 in response to a LOAD signal of the modulation control signal S8. The pulse width modulation circuit 33 generates pulse signals whose lengths correspond to the data that are held by the latch 32 using the PWM clock S9 as a reference in response to a START signal of the modulation control signal S8. The voltage of the pulse signals is amplified to Vm by the drive amplifier 34 and the modulation lines Dy1–Dyn of the display panel 1 are driven by the amplified pulse signals.
With the above operation, the content of the input video signal S1 is displayed on the display panel 1.